Learning VHDL: Get the lights and buttons working
Post date: Aug 22, 2015 8:49:52 PM
Up to this point, I had only been writing my hardware descriptions in Verilog. However, I recently started to learn the beginnings of VHDL for behavioral synthesis , and will much later dive into the world SystemVerilog. To give credit where credit is due, and for those who are simply interested in how I’m learning VHDL, my main sources are a blog created by Vipin, VHDL examples by Weijun Zhang, a quick VHDL tutorial created by Green Mountain Computing Systems, and the template VHDL sources provided in Xilinx ISE. There are other references, but the aforementioned ones was what got me started. The project discussed in this post is essentially the “Hello World” type of project, wherein the only goals can be summed up as first get the hardware and environment working smoothly and then write a hardware description that allows the user to interact with the hardware and see some lights blink.
The Atlys board!
The hardware in this case is the Digilent Atlys Spartan-6 Design Platform, an evaluation board equipped with the FPGA and the standard I/O, such as push buttons and LEDs. The design environment is Xilinx ISE 14.7, with which I have experience from my undergraduate days, doing projects with a Spartan 3E evaluation board all in Verilog. The hardware is programmed with the Digilent Adept System / Plug-in from ISE’s project navigator.
The eight LEDs show the output, whereas the four pushbuttons are for user input.
The project itself is simply a counter of which the user has control. The user can resume and pause the counter by toggling one of the pushbuttons, and reset the counter with another pushbutton. Two other pushbuttons can be utilized to either decrement or increment the counter while the counter is paused. The output is displayed through the eight LEDs in binary. The counter increments every second when running.
The code snippet of the process block above is taken from TopModule.vhd. The process block pretty much describes the functionality of the counter.
The sources are divided into the four entities, TopModule, Timer, Button, and Toggle. As its name suggests, the TopModule connects all other components together and reveals functionally how the counter is implemented. Timer raises a ready signal for a single clock cycle every specified period. Button raises a ready signal each time a button is pressed and released, thus preventing multiple button-related events from triggering if the button is held. Finally, Toggle can be either in a high or low state, which toggles every instance a button is pressed and then released.
All the sources are downloadable here, however the major functions of the counter can readily be interpreted from the Behavioral architecture’s process block of the TopModule. For larger projects in the future, I’ll most likely only post the source of the topmost entity to keep the size of theses posts to a minimum. For the next project in this series, I will attempt some signal processing and learn to implement systems with more than two states.