Memory Mapped AXI VGA Module on Zynq
Post date: Oct 26, 2015 3:3:57 PM
Project Snake. This project is really the beginning of a relatively larger project in which I have plans to implement an interactive game over Zynq. It’s not going to be an original since the focus of this project isn’t the game itself, but more the tools employed to develop and implement the game. The peripherals of importance on the ZedBoard will be the 4-bit VGA interface for graphics, pushbuttons for acquiring human input, and the audio codec for sound. Within the Zynq, both the programmable logic (PL) and the processing system (PS) will be employed. The significant components in the PL are the VGA module which maps a section of memory to the VGA interface and an Audio module that maps a FIFO buffer to the I2S interface. The software is going to be implemented over the PS’s application processor unit (APU) with PetaLinux.
Video demonstration of the game graphics project on the Avnet Zedboard.
A similar demonstration, except the application is updated to include bouncing squares and the demo itself is executing over the Digilent Zybo.
Game Graphics Project. But, for this smaller project, a simple program is demonstrated for the Xilinx Standalone operating system to test my memory-mapped AXI VGA module. I haven’t actually tried, but I’m certain Xilinx already provides the necessary IP for writing to a video interface from software (whether or not I have the licenses for the IP is another story). In addition to the VGA module, the test bench program itself is developed over the APU. The program randomly generates sixteen filled balls, with random radiuses and color, and then causes them to move in random directions, all at random speeds. A ball that collides with either another ball or the border of the monitor will bounce to the opposite direction.
To keep this entry short and sweet, I will only discuss the implementation of the VGA module. However, I will make the C source code freely available for the test bench program. The VGA module will also be posted on my GitHub. It should be noted the VGA module depends on Xilinx block ram.
VGA. It was fairly trivial to implement the module that directly drives the vsync and hsync signals, and the control signals indicating when the color data can be written to the color signals. I still got to give a lot of credit to Joseph Tarango for providing all the timing information on his site!
This table displays the timing information on which my VGA module relies. This table is referenced directly from Tarango’s page on the VGA interface!
The challenging aspect of the VGA module’s design was making it memory mapped. In order to have the VGA module access memory, my first thoughts were DMA, however I eventually opted for the direct implementation of the AXI4-Full interface, partly because I thought it would be a good opportunity to demonstrate how the interface operates in incremental burst mode, and partly because I believe this approach is faster.
The code snippet is an example on how to drive a read AXI4-Full interface in incremental mode, the mode of operation I think is likely most common when using the full AXI protocol. In incremental mode, the address space a transaction equates to the burst length, which is 256 in the case of my VGA module's master AXI4-Full interface.
The starting address is first transmitted over the address channel (i.e. signals prefixed with "m_axi_fb_ar") with handshaking synchronization, and then each word corresponding to subsequent addresses is read according to the handshaking signals in the read channel (i.e. signals prefixed with "m_axi_fb_r"). Not shown in the code snippet is where the words are stored after reception. The words are simply stored in block ram in a different behavioral block.
The general idea is each row of pixels is read from memory and then written to block ram in the VGA module during instances when the pixels aren’t being written to the VGA display. The row of data stored in block ram is finally written to the VGA display when pixels are being drawn. The process repeats itself for every row, and then resets back to the first row.
Please know that the buttons for zooming in and opening the PDF in its own window is located in the upper-right corner when scrolled to the top of the PDF! I apologize for the inconvenience.
Next Step. I had plans to write another testing program for PetaLinux, but I’m currently in the middle of setting up a computer to run Ubuntu. So, I may end up working on getting the ZedBoad’s audio codec operational, first.
Code. The description and corresponding driver for the VGA module can be found on my GitHub. The module is packaged as an "IP"; so, in order to instantiate the IP in a project, the project must be configured to recognize a local IP repository that includes the VGA module. At some point, I'll include an example design which should clear up any ambiguity.