Thesis: Zynq (TM)
The ZynqTM Project consists of the work I will be doing for my thesis as part of the System Chip Design Laboratory (SCDL), a research facility at Temple's College of Engineering that specializes in and strongly advocates for research in reconfigurable System-On-Chip (SOC) architectures, especially programmable logic (PL) such as Field Programmable Gate Arrays (FPGA). The trademarked term "Zynq" comes from the All Programmable (AP) technology on which the Zynq Project depends: The Zynq-7000 Extensible Processing Platform (EPP).
The Zynq-7000 EPP is an integrated circuit (IC) developed by Xilinx and that combines programmable logic (PL) with a processing system (PS) at the IC's center. Specifically, the programmable logic is a FPGA and the processing system is a Dual-core ARM Cortex-A9 processor which can run various Operating Systems (OS), including Real Time OSs (RTOS). The Zynq-7000 EPP's Dual-core ARM processor can support both Symmetric (SMP) and Asymmetric (AMP) Multiprocessing modes, though this project is only concerned with running the RTOS in AMP. Apart from the PL and PS, the Zynq EPP's also includes many peripheral interfaces and utilizes a SoC bus architecture built in accordance to the Advanced Microcontroller Bus Architecture (AMBA) Advance eXtensible Interface (AXI) 4 for communication among the Zynq EPP's ARM Cortex-A9 MPCore processor, FPGA fabric, and other inner-components. Xilinx has also released support for the Zynq EPP and other series 7 devices in the Vivado Design Suite, an Electronic Design Automation (EDA) that provides many powerful tools for analyzing and enhancing hardware performance and High Level Behavioral Synthesis (HLS), the process of converting an algorithm written in a Hardware Description Language (HDL) to a digital form that carries out the same behavior. Xilinx's Software Development Kit (SDK) is the integrated development environment intended for the Zynq EPP's (i.e. ARM processor) software development in C or C++.
Overhead picture of the ZC702 Evaluation Board
Project Goal: As of now, the main objective on the Zynq Project is to analyze, and then later improve, the performance of the Zynq EPP's AMBA bus under applications that demand strict timing requirements and the transfer of large of amounts of information. In addition to those demands, many applications require information transmitted over the bus to have higher priority than other information. With the goal of the project in mind, the first set of steps will be to program a Zynq-7000 EPP's Dual-core ARM Cortex-A9 MPCore processor to run in AMP mode with FreeRTOS as the RTOS for both cores, using Xilinx's Vivado Design Suite and SDK. The model of the Zynq-7000 EPP that will be configured is the Z-7020. The development board on which the Z-7020 runs for this project is the Zynq-7000 EPP ZC702 Evaluation Kit. The primary task thereafter will be to analyze the performance of the Zynq EPP's interconnect while each core of the ARM processor executes their respective tasks, while simultaneously communicating with each other and with other components within the Zynq EPP.
2. Configuring constraint files and interfacing modules with Zynq Processing System - Oct 05, 2013 6:47:55 PM