Simple Blazing FIR SoC Project on the Nexys 4
Post date: May 16, 2016 9:25:7 PM
Video demonstration of the project.
Simple Blazing FIR. As explained in the video, the Simple Blazing FIR SoC system captures audio samples with a microphone and outputs the volume of the audio's bass as a varying pulse across a set of LEDs. The project is developed over the Digilent Nexys 4 DDR board and uses the Digilent PmodMIC to capture the audio samples. On the Nexys 4's Artix-7 FPGA is a SoC controlled by a Microblaze MCU and other soft peripherals. To keep this post brief, the system is described from a high-level point of view. Details can be found from the project file, whose repository can be found at the end of this post.
It should be noted that this project could have been reduced to several HDL modules, likely saving resources and improving performance. However, the focus of this project was to primarily get some experience with the Xilinx AXI DMA IP core as an alternative way to have a peripheral device to access memory and to become more reliant on reusable IP and code. Thus, in addition to the DMA core, this project also demonstrates the usage of the AXI Timer, FIR Compiler, and AXI Quad SPI IP.
Black represents the controller. Gray are the other IP cores. Light-blue are the interconnecting routers and AXI-based interfaces. Finally, blue signifies interfaces external to the Artix. Not shown are the clock signals, resets, interrupt controller / interrupts, and several other logic.
System. The figure shown above is an abstraction of the programmable logic, excluding the cores and signals that don't explain how the system works, functionally. The Microblaze acts as the system's controller but whose operations only execute on reaction to the AXI Timer's interrupt, which triggers according to a sample rate of 44.1 KHz. Every sample period, the Microblaze starts the AXI Quad SPI such that a 12-bit sample is acquired from the PmodMIC. On completion, another interrupt causes the Microblaze to buffer each audio sample in either one of two buffers located in block RAM. Filled buffers are finally transmitted to the FIR Compiler with the AXI DMA.
The 49 order FIR Compiler itself is configured so that its coefficients pass frequencies that roughly range from 0 to 300 Hz, the bass frequencies. The output samples pass into a custom module that sets the LEDs of the Nexys according to thresholds. These thresholds are automatically determined by the possible value range of each output sample.
Sources. The link to the GitHub repository can be accessed here.